The present invention relates to a phase change memory device, and more particularly, to a phase change memory device that allows a plurality of memory cells of a memory array to be programmed with the same reset current and the same set current.
In general, memory devices are largely categorized as a volatile RAM (random access memory) that loses stored information when power is interrupted and a non-volatile ROM (read-only memory) that can continuously maintain the stored state of information even when power is interrupted. Volatile RAM includes memory such as DRAM (dynamic RAM) and SRAM (static RAM) whereas non-volatile ROM includes a flash memory device such as an EEPROM (electrically erasable and programmable ROM) can be mentioned.
As is well known in the art, although the DRAM is an excellent memory device, the DRAM must have a high charge storing capacity. To this end, since the surface area of an electrode must be increased, it is difficult to obtain a high integration level. Further, in a flash memory device, a high operation voltage is required when compared to a source voltage due to the fact that two gates are stacked on each other. Accordingly, since a separate booster circuit is needed to form the voltage necessary for write and delete operations, it is difficult to accomplish a high integration level.
Due to these limitations, research to develop a novel memory device having a simple configuration capable of accomplishing a high level of integration while retaining the characteristics of a non-volatile memory device have been pursued. For example, recently, a phase change memory device has been disclosed in the art.
The phase change memory device is based on the fact that a phase change occurs in a phase change layer interposed between a lower electrode and an upper electrode from a crystalline state to an amorphous state due to current flow between the lower electrode and the upper electrode. The information stored in a cell is recognized by the medium of a difference in resistance between the crystalline state and the amorphous state.
The phase change memory device includes a chalcogenide layer which is a compound layer made of germanium (Ge), stibium (Sb) and tellurium (Te) that is employed as a phase change layer. As a current is applied, the phase change layer undergoes a phase change between the amorphous state and the crystalline state due to heat, specifically Joule heat. Accordingly, in the phase change memory device, the specific resistance of the phase change layer in the amorphous state is higher than the specific resistance of the phase change layer in the crystalline state. Considering this fact, in a read mode, sensing the current flowing through the phase change layer determines whether the information stored in the phase change cell has a logic value of ‘1’ or ‘0’.
Meanwhile, in a memory array having a plurality of memory cells, the parasitic loadings of the respective memory cells can be different from one another according to the locations of the memory cells in the memory array. The parasitic loadings induce differences in the reset currents of the memory cells as the area of the memory array increases. These differences in the reset currents may also cause differences in set currents.
Due to the differences in set currents, all the memory cells cannot be uniformly set by one set current. That is to say, while some of the memory cells transition to a set state by the set current, other memory cells can be in a reset state. Even where some of the memory cells transition to the set state, the values of set resistances can be different from one another.
FIG. 1 is a graph illustrating a relationship between the current applied to phase change cells and the resistances of the phase change cells in a conventional phase change memory device.
Referring to FIG. 1, respective memory cells have different reset and set current curves. The first cell has a high set current, the second cell has an intermediate set current, and the third cell has a low set current.
If the current corresponding to a voltage level (V) is applied to the respective cells, the second cell and the third cell transition to reset resistance states. The values of the reset resistances of the second and third cells are also different from each other.
Therefore, as described above, in a plurality of memory arrays, the amount of set current for transitioning the phase change cells to a set state may vary in respective memory cells. Thus, all the memory cells may not transition to the set state by one set is current.
The differences in the amount of set current for the memory cells are generally observed between the cell (a first cell) closest to a sense amplifier and the cell farthest from the sense amplifier (an nth cell). In the case of the first cell, the first cell can be over-programmed when compared to the nth cell, and in the case of the nth cell, the nth cell may not be programmed.